Intermediate Topic 33 of 51 Computer Architecture & Logic
Branch Prediction
Guessing branch outcomes to keep the pipeline full.
How it works
A branch predictor guesses the outcome of a conditional branch before it is resolved so that the pipeline can keep fetching instructions. Simple schemes use a saturating 2-bit counter per branch; more advanced ones correlate with global history, as in gshare and TAGE, or use neural predictors. A branch target buffer predicts the destination address. A wrong guess flushes the pipeline, costing 10 to 20 cycles.
Step-by-step walkthrough
- The CPU meets a conditional branch before knowing the result.
- A predictor looks at history to guess.
- It guesses taken and fetches from the target at once.
- If the guess is right no time is lost.
- If wrong the pipeline is flushed and 10 to 20 cycles are wasted.
Where it is used
Every high-performance CPU relies on prediction, achieving over 95 percent accuracy on typical code. Programmers write predictable branches, use branchless code or sort data to improve speed in hot loops.
Common pitfall
Unpredictable data-dependent branches, such as in a loop over random values, are slow. Prediction mistakes were exploited in Spectre-style attacks, because speculative work leaves traces in caches. Do not assume a branch is free; measure with performance counters and consider conditional moves.
Where it fits in the course
Branch Prediction is topic 33 of 51 in Computer Architecture & Logic, rated Intermediate. It follows Pipeline Hazards. The next topic is Out-of-Order Execution.
Practice and explore
- Open the interactive lesson, with a mini quiz.
- Take the Computer Architecture & Logic quiz.
How to study this topic
- Read the explanation above and restate the definition in your own words.
- Open the interactive lesson and answer its mini quiz.
- Read the common pitfall, then write a short example that avoids it.
- Check your understanding in the Computer Architecture & Logic quiz, and revisit the topic if you miss a question.
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Related topics
- Pipeline Hazards (Computer Architecture & Logic)
- Out-of-Order Execution (Computer Architecture & Logic)
- Instruction Pipelining (Computer Architecture & Logic)
- Superscalar Processors (Computer Architecture & Logic)