Advanced Topic 43 of 51 Computer Architecture & Logic
Bus Architecture
Shared pathways carrying data, address and control signals.
How it works
A bus is a shared set of wires and protocol that carries addresses, data and control signals between components such as the CPU, memory and I/O devices. Parallel buses send many bits at once, while modern high-speed links like PCIe and USB use serial point-to-point lanes. Arbitration decides who may use a shared bus, and bandwidth is set by width and clock rate.
Step-by-step walkthrough
- The bus is a shared set of wires.
- Address lines say where, data lines carry values, control lines say read or write.
- Memory answers the request.
- Only one master may drive the bus at a time, so arbitration is needed.
- Modern chips use point-to-point links to avoid the sharing bottleneck.
Where it is used
Connecting processors to memory, peripherals to the system, chips on a board and components inside systems-on-chip, as with AMBA and I2C, SPI and CAN buses, use bus designs.
Common pitfall
A shared bus becomes a bottleneck as devices increase, which is why modern designs favor switched point-to-point fabrics. Signal integrity and skew limit parallel bus speed. Incorrect arbitration can cause starvation. Mismatched protocols or voltages between devices cause failures, so check specifications.
Where it fits in the course
Bus Architecture is topic 43 of 51 in Computer Architecture & Logic, rated Advanced. It follows Interrupts. The next topic is Storage Devices.
Practice and explore
- Open the interactive lesson, with a mini quiz.
- Take the Computer Architecture & Logic quiz.
How to study this topic
- Read the explanation above and restate the definition in your own words.
- Open the interactive lesson and answer its mini quiz.
- Read the common pitfall, then write a short example that avoids it.
- Check your understanding in the Computer Architecture & Logic quiz, and revisit the topic if you miss a question.
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