LearnViz CompSci
Home / Learn / Computer Architecture & Logic / Cache Coherence

Advanced Topic 38 of 51 Computer Architecture & Logic

Cache Coherence

Keeping copies of shared data consistent across cores.

How it works

Cache coherence ensures that all cores see a consistent view of memory when each has its own cache holding copies of the same line. Protocols such as MESI track each line as Modified, Exclusive, Shared or Invalid. Snooping protocols broadcast changes on a bus or interconnect, while directory-based protocols track sharers for larger systems. A write invalidates or updates other copies.

Step-by-step walkthrough

  1. Both cores read x = 5 into their caches.
  2. Core 2 reads the same line.
  3. Core 1 writes x = 6 and invalidates other copies.
  4. Core 2's next read misses and gets the updated value.
  5. The MESI protocol tracks lines as Modified, Exclusive, Shared or Invalid.

Where it is used

All multicore and multiprocessor systems implement coherence in hardware, which makes shared-memory programming possible without manual cache flushes. It underlies the behavior of locks and atomic operations.

Common pitfall

Coherence traffic is costly: false sharing, where independent variables sit on the same cache line, makes cores fight over ownership and slows programs dramatically. Coherence does not by itself define ordering between different addresses; that is the memory consistency model. Pad hot variables to separate cache lines.

Where it fits in the course

Cache Coherence is topic 38 of 51 in Computer Architecture & Logic, rated Advanced. It follows Multicore Processors. The next topic is SIMD and Vector Processing.

Practice and explore

How to study this topic

  1. Read the explanation above and restate the definition in your own words.
  2. Open the interactive lesson and answer its mini quiz.
  3. Read the common pitfall, then write a short example that avoids it.
  4. Check your understanding in the Computer Architecture & Logic quiz, and revisit the topic if you miss a question.

Frequently asked questions

What is Cache Coherence?
Keeping copies of shared data consistent across cores. It belongs to Computer Architecture & Logic and is an advanced-level topic.
Where do people use Cache Coherence?
All multicore and multiprocessor systems implement coherence in hardware, which makes shared-memory programming possible without manual cache flushes.
What is the most common mistake with Cache Coherence?
Coherence traffic is costly: false sharing, where independent variables sit on the same cache line, makes cores fight over ownership and slows programs dramatically.
What should I learn before this topic?
Start with Multicore Processors, the topic just before it in Computer Architecture & Logic.
How can I practice it?
Answer the mini quiz in the interactive lesson, then take the Computer Architecture & Logic quiz.
Is Cache Coherence hard to learn?
It is an Advanced topic. Expect to read the explanation more than once and to connect it with earlier topics. Working through a small example by hand helps most.
How long does it take to learn Cache Coherence?
Most learners can read the explanation and finish the interactive lesson in under an hour. Fluency comes from applying the idea, so plan a few short practice sessions with the quiz.
Which topics are related to Cache Coherence?
Multicore Processors, SIMD and Vector Processing, Speculative Execution are closely connected. The full list is in the related topics section of this page.
What should I study after Cache Coherence?
Continue with SIMD and Vector Processing, the next topic in Computer Architecture & Logic.

Related topics