Advanced Topic 42 of 52 Data Structures
LRU Cache Structure
Hash map plus linked list evicting least recently used entries.
How it works
An LRU cache combines a hash map, mapping keys to list nodes, with a doubly linked list ordered by recency. Accessing a key moves its node to the front; when the cache is full, the node at the tail, the least recently used one, is evicted. Both get and put run in O(1) time, which is why this pairing is the standard design.
Step-by-step walkthrough
- get(k) finds the node in the hash map in O(1).
- The node is moved to the front of the linked list as most recently used.
- put(k) with a full cache evicts the tail node.
- The evicted key is removed from the map too.
- The new key is inserted at the front.
Where it is used
Web browsers, database buffer pools, operating-system page caches, CDN edge servers and memoization layers use LRU eviction. Libraries offer ready-made implementations.
Common pitfall
Forgetting to update recency on reads, or leaving a stale map entry after eviction, breaks correctness. Not thread-safe by default: concurrent access needs locks. Scans of large datasets can flush useful entries, so consider variants such as LRU-K or 2Q.
Where it fits in the course
LRU Cache Structure is topic 42 of 52 in Data Structures, rated Advanced. It follows Quadtrees. The next topic is Circular Buffer.
Practice and explore
- Open the interactive lesson, with a mini quiz.
- Take the Data Structures quiz.
How to study this topic
- Read the explanation above and restate the definition in your own words.
- Open the interactive lesson and answer its mini quiz.
- Read the common pitfall, then write a short example that avoids it.
- Check your understanding in the Data Structures quiz, and revisit the topic if you miss a question.
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Related topics
- Quadtrees (Data Structures)
- Circular Buffer (Data Structures)
- KD-Trees (Data Structures)
- Persistent Data Structures (Data Structures)
- Cache Memory (Computer Architecture & Logic)
- Cache Mapping (Computer Architecture & Logic)
- Cache Replacement Policies (Computer Architecture & Logic)