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Advanced Topic 50 of 51 Concurrency & Parallelism

Hardware Transactional Memory

CPU support for optimistic atomic regions.

How it works

Hardware transactional memory lets the processor execute a region of code speculatively as an atomic transaction: reads and writes are tracked in the cache, and if no conflicting access from another core occurs, the transaction commits all changes at once; otherwise it aborts and rolls back. Intel TSX offered restricted transactional memory with xbegin and xend and hardware lock elision, IBM POWER and Z have versions, and ARM defined TME. A fallback path using a lock is required because transactions can always abort.

Where it is used

Elision of coarse locks to run critical sections concurrently when they do not conflict, speeding up concurrent data structures and databases, was the main use.

Common pitfall

Transactions abort for capacity overflow of the cache, interrupts, system calls and conflicts, so they only work for small, short regions. Security issues led Intel to disable TSX on many processors. Performance can be unpredictable and fallback paths must be correct. Support is limited and inconsistent across vendors, so it is rarely relied on in portable software.

Where it fits in the course

Hardware Transactional Memory is topic 50 of 51 in Concurrency & Parallelism, rated Advanced. It follows Memory Models in Languages. The next topic is Performance Scaling Analysis.

Practice and explore

How to study this topic

  1. Read the explanation above and restate the definition in your own words.
  2. Open the interactive lesson and answer its mini quiz.
  3. Read the common pitfall, then write a short example that avoids it.
  4. Check your understanding in the Concurrency & Parallelism quiz, and revisit the topic if you miss a question.

Frequently asked questions

What is Hardware Transactional Memory?
CPU support for optimistic atomic regions. It belongs to Concurrency & Parallelism and is an advanced-level topic.
Where do people use Hardware Transactional Memory?
Elision of coarse locks to run critical sections concurrently when they do not conflict, speeding up concurrent data structures and databases, was the main use.
What is the most common mistake with Hardware Transactional Memory?
Transactions abort for capacity overflow of the cache, interrupts, system calls and conflicts, so they only work for small, short regions.
What should I learn before this topic?
Start with Memory Models in Languages, the topic just before it in Concurrency & Parallelism.
How can I practice it?
Answer the mini quiz in the interactive lesson, then take the Concurrency & Parallelism quiz.
Is Hardware Transactional Memory hard to learn?
It is an Advanced topic. Expect to read the explanation more than once and to connect it with earlier topics. Working through a small example by hand helps most.
How long does it take to learn Hardware Transactional Memory?
Most learners can read the explanation and finish the interactive lesson in under an hour. Fluency comes from applying the idea, so plan a few short practice sessions with the quiz.
Which topics are related to Hardware Transactional Memory?
Memory Models in Languages, Performance Scaling Analysis, Linearizability are closely connected. The full list is in the related topics section of this page.
What should I study after Hardware Transactional Memory?
Continue with Performance Scaling Analysis, the next topic in Concurrency & Parallelism.

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