Intermediate Topic 19 of 51 Computer Architecture & Logic
Finite State Machines in Hardware
Hardware controllers moving between defined states.
How it works
A finite state machine in hardware is a state register plus two blocks of combinational logic: one computing the next state from the current state and inputs, and one computing outputs. A clock updates the register. Designers draw a state diagram, assign binary codes to states, derive the logic and implement it with flip-flops. Encodings such as binary, Gray and one-hot trade area against speed.
Step-by-step walkthrough
- The controller starts in the Idle state.
- A start input moves it to Request.
- The grant signal moves it to Busy.
- Work finishes and it enters Done.
- A reset returns it to Idle.
Where it is used
Protocol controllers, traffic lights, vending machines, UART and bus interfaces, instruction decoding control units and pattern detectors use hardware state machines.
Common pitfall
Unspecified transitions leave undefined behavior, and illegal states left unused can trap a circuit after a glitch, so add recovery. Mixing Mealy outputs with asynchronous inputs can create glitches. Register outputs for clean timing, give every state a default transition and always define a reset state.
Where it fits in the course
Finite State Machines in Hardware is topic 19 of 51 in Computer Architecture & Logic, rated Intermediate. It follows Sequential Circuits. The next topic is Arithmetic Logic Unit.
Practice and explore
- Open the interactive lesson, with a mini quiz.
- Take the Computer Architecture & Logic quiz.
How to study this topic
- Read the explanation above and restate the definition in your own words.
- Open the interactive lesson and answer its mini quiz.
- Read the common pitfall, then write a short example that avoids it.
- Check your understanding in the Computer Architecture & Logic quiz, and revisit the topic if you miss a question.
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