Advanced Topic 38 of 51 Concurrency & Parallelism
GPU Memory Hierarchy
Global, shared and register memory on GPUs.
How it works
GPUs have a multi-level memory hierarchy with different sizes, latencies and scopes. Registers are fastest and private to each thread; shared memory is a small, fast, programmer-managed scratchpad shared by threads of a block; L1 and L2 caches reduce traffic; global memory, the large off-chip DRAM or HBM, has high bandwidth but hundreds of cycles of latency; constant and texture memory offer cached read-only access; and local memory spills registers to global memory. Accesses by a warp coalesce into few transactions when addresses are contiguous.
Where it is used
Optimizing CUDA and OpenCL kernels, such as tiled matrix multiplication that stages data in shared memory, depends on exploiting this hierarchy.
Common pitfall
Uncoalesced or strided access wastes bandwidth, shared-memory bank conflicts serialize accesses and register pressure reduces occupancy or causes spills. Data transfers between host and device are much slower than on-device memory. Forgetting synchronization when threads share data in shared memory causes races. Profile memory throughput and restructure data layouts, such as structure of arrays.
Where it fits in the course
GPU Memory Hierarchy is topic 38 of 51 in Concurrency & Parallelism, rated Advanced. It follows CUDA Programming. The next topic is Parallel Sorting.
Practice and explore
- Open the interactive lesson, with a mini quiz.
- Take the Concurrency & Parallelism quiz.
How to study this topic
- Read the explanation above and restate the definition in your own words.
- Open the interactive lesson and answer its mini quiz.
- Read the common pitfall, then write a short example that avoids it.
- Check your understanding in the Concurrency & Parallelism quiz, and revisit the topic if you miss a question.
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Related topics
- CUDA Programming (Concurrency & Parallelism)
- Parallel Sorting (Concurrency & Parallelism)
- MPI (Concurrency & Parallelism)
- Load Balancing in Parallel Programs (Concurrency & Parallelism)
- Memory Hierarchy (Computer Architecture & Logic)
- Manual Memory Management (Languages & Compilers)
- Memory Constraints (Mobile, Embedded & IoT)