Intermediate Topic 27 of 51 Computer Architecture & Logic
Cache Mapping
Direct, set-associative and fully associative placement policies.
How it works
Cache mapping decides which cache lines a memory block may occupy. In a direct-mapped cache each block maps to exactly one line, determined by the index bits of the address; in a fully associative cache it can go anywhere; in an n-way set-associative cache it maps to one set and can occupy any of n lines within it. The address splits into tag, index and offset fields.
Step-by-step walkthrough
- Direct mapped: each memory block has exactly one possible line.
- Blocks 0 and 4 both want line 0 and keep evicting each other.
- Set associative: a block may go in any way of its set.
- Both blocks can now stay in the cache.
- Fully associative allows any line but needs the most comparators.
Where it is used
CPU caches mostly use set-associative designs, which balance cost and conflict misses. TLBs and some software caches use similar mappings. Understanding the tag, index and offset helps compute hit rates in exam problems and in performance analysis.
Common pitfall
Direct-mapped caches suffer conflict misses when two hot addresses map to the same line. Higher associativity reduces conflicts but increases latency, area and power. Miscomputing the number of index bits is a common error. Power-of-two array strides can alias to the same sets.
Where it fits in the course
Cache Mapping is topic 27 of 51 in Computer Architecture & Logic, rated Intermediate. It follows Cache Memory. The next topic is Cache Replacement Policies.
Practice and explore
- Open the interactive lesson, with a mini quiz.
- Take the Computer Architecture & Logic quiz.
How to study this topic
- Read the explanation above and restate the definition in your own words.
- Open the interactive lesson and answer its mini quiz.
- Read the common pitfall, then write a short example that avoids it.
- Check your understanding in the Computer Architecture & Logic quiz, and revisit the topic if you miss a question.
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Related topics
- Cache Memory (Computer Architecture & Logic)
- Cache Replacement Policies (Computer Architecture & Logic)
- Memory Hierarchy (Computer Architecture & Logic)
- Virtual Memory in Hardware (Computer Architecture & Logic)
- Texture Mapping (Graphics, Vision & Media)
- LRU Cache Structure (Data Structures)