Intermediate Topic 28 of 51 Computer Architecture & Logic
Cache Replacement Policies
Rules like LRU deciding which block to evict.
How it works
When a set is full and a new block must be loaded, the replacement policy picks a victim. Least recently used evicts the block untouched for the longest time, exploiting temporal locality; FIFO evicts the oldest; random picks any; pseudo-LRU approximates LRU cheaply with a few bits; and LFU evicts the least frequently used. Belady's optimal policy evicts the block used furthest in the future and serves as a benchmark.
Step-by-step walkthrough
- The cache holds A B C D and is full.
- Access A, it becomes most recently used.
- Access C, B and D are now the least recently used.
- A miss for E must evict a line.
- LRU evicts the oldest-used line B, FIFO evicts the oldest-loaded and random picks any.
Where it is used
CPU caches, operating-system page replacement, database buffer pools, CDN and web caches all choose a policy. Real hardware often uses tree-based pseudo-LRU.
Common pitfall
True LRU is expensive to implement in hardware for high associativity. Sequential scans larger than the cache flush useful data under LRU. FIFO can show Belady's anomaly, where more capacity gives more misses. Match the policy to the workload and measure hit rates.
Where it fits in the course
Cache Replacement Policies is topic 28 of 51 in Computer Architecture & Logic, rated Intermediate. It follows Cache Mapping. The next topic is Virtual Memory in Hardware.
Practice and explore
- Open the interactive lesson, with a mini quiz.
- Take the Computer Architecture & Logic quiz.
How to study this topic
- Read the explanation above and restate the definition in your own words.
- Open the interactive lesson and answer its mini quiz.
- Read the common pitfall, then write a short example that avoids it.
- Check your understanding in the Computer Architecture & Logic quiz, and revisit the topic if you miss a question.
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Related topics
- Cache Mapping (Computer Architecture & Logic)
- Virtual Memory in Hardware (Computer Architecture & Logic)
- Cache Memory (Computer Architecture & Logic)
- TLB (Computer Architecture & Logic)
- Page Replacement Algorithms (Operating Systems)
- LRU Cache Structure (Data Structures)